This invention relates to a semiconductor device comprising a vertical insulated gate field effect device, in particular an insulated gate field effect device in which the insulated gate is formed within a recess extending into a semiconductor body, and to a method of manufacturing such a device.
As used herein the term "vertical insulated gate field effect device" means an insulated gate field effect device in which the main current path is between two opposed major surfaces of the semiconductor body.
U.S. Pat. No. 5,072,266 describes a vertical insulated gate field effect device of this type. In particular, U.S. Pat. No. 5,072,266 describes a power MOSFET which consists of many parallel-connected insulated gate field effect device cells formed within a first region adjacent one major surface of the semiconductor body with the first region providing a conductive path to a main electrode formed on the other major surface of the semiconductor body. Each device cell consists of a second semiconductor region of the opposite conductivity type formed within the first region adjacent the one major surface, a third semiconductor region forming with the second region a pn junction meeting the one major surface and a recess extending through the second and third regions into the first region. The recesses of the device cells are connected together to define a continuous trench within which a continuous insulated gate structure is provided for controlling conduction along conduction channel regions of the second regions bounding the trench.
The use of such a structure to form an insulated gate field effect device such as a power MOSFET enables, for a given conduction channel length, higher device cell packing densities to be achieved than can be attained using a planar structure, that is a structure in which the insulated gate is formed on the one major surface. However, in such a structure the point at which breakdown will occur will generally be adjacent the trench because of the high electric fields which can arise at sharp edges or corners of the trench. This can cause problems such as hot charge carrier injection into the gate insulating layer which could result in degradation of the device performance and may exacerbate the possibility of destructive bipolar breakdown, especially when switching an inductive load. U.S. Pat. No. 5,072,266 aims to overcome or at least reduce these problems by providing each second region with a more highly doped highly curved subsidiary region which is located away from the conduction channel regions centrally of the device cell bounded by the trench and which extends into the first region further than the trench so that when a critical voltage is exceeded breakdown of the device occurs in the bulk of the semiconductor body in the vicinity of the reverse-biassed pn junction between the central highly doped subsidiary region of the second region and the first region.
Thus the point of initation of avalanche breakdown is moved away from the trench reducing the possibility of hot charge carrier injection into the gate insulating layer. Moving the point of initiation of avalanching into the bulk of the semiconductor device should be of advantage where the device is to be used for switching an inductive load because higher currents can be carried within the bulk of the semiconductor body thus enabling faster dissipation of the excessive energy resulting from the rapid rise in voltage across the device which may occur during the switching of an inductive load than is possible where avalanching is initiated adjacent a recessed insulated gate structure.
As described in U.S. Pat. No. 5,072,266, the more highly doped subsidiary region of the second region is formed by introducing impurities through a first mask and subsequent second and third masks are used to introduce the impurities to form the conduction channel defining region of the second region and the third region and to form the trench. It is of course necessary to allow for misalignment tolerances between these three separate masks which inevitably places a restriction on the minimum device dimensions or design rules and, moreover, misalignments which may occur may make some of the device cells less rugged, that is more susceptible to breakdown by parasitic bipolar action, than the other device cells. Also alignment problems may affect the reproducibility of device characteristics between different processing batches. Moreover, the formation of the central highly doped subsidiary region of the second region requires high doping concentrations and long diffusion or drive-in times and it may prove difficult to control the precise depth and curvature of the central more highly doped subsidiary region which will affect the precise voltage at which breakdown will occur and thus also exacerbate reproducibility problems. Furthermore because these portions are highly doped and deep, there may be more possibility of encroachment on the conduction channel regions which would adversely affect the device threshold voltage. In addition, the extension of the central highly doped subsidiary region into the generally lowly doped drain drift region may make the device more susceptible to punchthrough, thus making the breakdown voltage more sensitive to the precise thickness and doping of the first region which is generally-an epitaxial layer. Again the characteristics of the first region may vary from batch to batch.